To know
about the advantages of TTL logic family, one should have a basic idea about
RTL, DTL etc. Diode logic (DL) uses diodes to implement logical functions like
AND and OR. But the disadvantage is that it can not perform NOT operation. As
AND and OR are not complete functions by themselves, they can not perform
several logic functions without NOT. Hence, there was a need for some device
which can perform a NOT function as diodes can not. That device is a
transistor. Then came the DTL which uses a transistor along with diodes. As a
transistor can act as an inverter, NAND (NOT-AND) & NOR (NOT-OR) operations
can be performed. But this logic uses several diodes which will slow down its
operation. Due to the delay offered by them, the logic levels may sometimes
change i. e. 0 t0 1 or 1 to 0. Then came TTL. This logic uses a multi emitter
transistor, a transistor with many emitter terminals. As every emitter is
nothing but a diode, this logic eliminates the use of all diodes. This is the
major advantage. As transistor becomes ON and OFF much rapidly than a diode,
switching time will be faster.
TTL, or Transistor-transistor logic replaced resistor-transistor logic, and used much less power. The TTL family is very fast and reliable, and newer faster, less power-consuming, etc. types are always being developed.
TTL, or Transistor-transistor logic replaced resistor-transistor logic, and used much less power. The TTL family is very fast and reliable, and newer faster, less power-consuming, etc. types are always being developed.
ECL is Emitter Coupled Logic. Compare with TTL which turned
the transistors completely on (saturated) or off for the two states. Changing
from the off state or the saturation state requires significant time. In ECL
the transistors are biased so they operate near the middle of their range and
coduct a little more or a little less for their states. ECL is faster than TTL,
very power hungry in comparison, and were used in many early mini and main
frame computers for speed. I believe that CMOS has eclipsed ECL in speed, and
certainly consusmes much less power.
ECL is fastest among the three because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the
storage time is eliminated.
The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Non-saturated Logic: In Non-saturated Logic, the transistors are not driven into saturation.
(i) Schottky TTL
(ii) Emitter Coupled Logic (ECL)
Characteristics of CMOS logic:
1. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate.
2. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS.
3. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays.
4. Noise immunity approaches 50% or 45% of the full logic swing.
5. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high.
Characteristics of TTL logic:
1. Power dissipation is usually 10 mW per gate.
2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.
CMOS compared to TTL:
1. CMOS components are typically more expensive that TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation.
3. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design.
4. Due to longer rise and fall times, the transmission of digital signals become simpler and less expensive with CMOS chips.
5. CMOS components are more susceptible to damage from electrostatic discharge than TTL compenents.
storage time is eliminated.
The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Non-saturated Logic: In Non-saturated Logic, the transistors are not driven into saturation.
(i) Schottky TTL
(ii) Emitter Coupled Logic (ECL)
Characteristics of CMOS logic:
1. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate.
2. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS.
3. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays.
4. Noise immunity approaches 50% or 45% of the full logic swing.
5. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high.
Characteristics of TTL logic:
1. Power dissipation is usually 10 mW per gate.
2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.
CMOS compared to TTL:
1. CMOS components are typically more expensive that TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation.
3. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design.
4. Due to longer rise and fall times, the transmission of digital signals become simpler and less expensive with CMOS chips.
5. CMOS components are more susceptible to damage from electrostatic discharge than TTL compenents.
Excellent job!!! Very well written which clears basic concepts. Keep it up and carry on.
ReplyDeleteperfect explanation
ReplyDeleteGood explanation 👍
ReplyDeleteGood explanation 👍
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ReplyDeleteWhich is faster among ECL and schottky TTL because both are non saturated logic family.
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